/*
    Copyright (c);2019-2022;Wiscom System;

	All rights reserved.

    Redistribution and use in source and binary forms, with or without modification,
are permitted provided that the following conditions are met:

    1. Redistributions of source code must retain the above copyright notice, this
       list of conditions and the following disclaimer.
    2. Redistributions in binary form must reproduce the above copyright notice,
       this list of conditions and the following disclaimer in the documentation
       and/or other materials provided with the distribution.
    3. Neither the name of the Wiscom System nor the names of its contributors
       may be used to endorse or promote products derived from this software without
       specific prior written permission.

    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
OF SUCH DAMAGE.
*/

#include "los_sem.h"
#include "los_base.ph"
#include "los_hwi.h"
#include "los_api_irqres.h"
#include "los_inspect_entry.h"
#include "csg_sdk_hal.h"
#ifdef LOSCFG_LIB_LIBC
#include "string.h"
#endif
#include "mytypes.h"
#include "pca9555.h"
#include "csg_libopt.h"


#define HOST_WRITE_COMMAND 0x00
#define HOST_READ_COMMAND  0x01

#define INPUT_PORT_REGISTER0                    0x00   /* 输入端口寄存器0，负责IO00-IO07 */
#define INPUT_PORT_REGISTER1                    0x01   /* 输入端口寄存器1，负责IO10-IO17 */
#define OUTPUT_PORT_REGISTER0                   0x02   /* 输入端口寄存器0，负责IO00-IO07 */
#define OUTPUT_PORT_REGISTER1                   0x03   /* 输入端口寄存器1，负责IO10-IO17 */
#define POLARITY_INVERSION_PORT_REGISTER0       0x04   /* 输入端口寄存器0，负责IO00-IO07 */
#define POLARITY_INVERSION_PORT_REGISTER1       0x05   /* 输入端口寄存器1，负责IO10-IO17 */
#define CONFIG_PORT_REGISTER0                   0x06   /* 输入端口寄存器0，负责IO00-IO07 */
#define CONFIG_PORT_REGISTER1                   0x07   /* 输入端口寄存器1，负责IO10-IO17 */

#define GPIO_PORT0 0
#define GPIO_PORT1 1

uint8_t nca9555_write_byte(uint8_t addr, uint8_t command, uint8_t write_register_data)
{
    Pca9555SendData(&write_register_data, command, 1); //addr unuse
}
uint8_t nca9555_read_byte(uint8_t slave_num, uint8_t addr, uint8_t read_register_data, uint8_t *read_data)
{
    Pca9555ReceData(read_data, read_register_data, 1); //slave_num、addr unuse
}
void lwip_iomux_cfg(void)
{
    iomux_ls_iof_oval_cfg(IOMUX_BASE, XEC_MDC_IOF_OVAL , 11, XEC_MDC_HS_SEL , 0 , 0);

    iomux_ls_iof_oval_cfg(IOMUX_BASE, XEC_MDIO_IOF_OVAL , 12, XEC_MDIO_HS_SEL , 0 , 0);
    iomux_ls_iof_ival_cfg(IOMUX_BASE, XEC_MDIO_IOF_IVAL , 12, XEC_MDIO_HS_SEL, 0, 0);
    //  iomux_ls_iof_inv_cfg(IOMUX_BASE, XEC_XMII_TXC_IOF_IVAL, XEC_XMII_TXC_HS_SEL ,0,0);
     
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_XMII_TXC_IOF_IVAL , 0, XEC_XMII_TXC_HS_SEL ,0 , 0);
    // iomux_ls_iof_inv_cfg(IOMUX_BASE, XEC_GMII_RXC_IOF_OVAL, XEC_GMII_RXC_HS_SEL ,0,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXC_IOF_OVAL , 0, XEC_GMII_RXC_HS_SEL, 0,  0);
    iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXEN_IOF_OVAL , 0, XEC_GMII_TXEN_HS_SEL , 0 , 0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXDV_IOF_OVAL , 0, XEC_GMII_RXDV_HS_SEL, 0, 0);

    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXER_IOF_OVAL , 0, XEC_GMII_TXER_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXER_IOF_IVAL , 0, XEC_GMII_RXER_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_CRS_IOF_IVAL , 0, XEC_GMII_CRS_HS_SEL, 0, 0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_COL_IOF_IVAL , 0, XEC_GMII_COL_HS_SEL, 0, 0);

     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT0_IOF_OVAL ,0, XEC_GMII_TXD_BIT0_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT0_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT1_IOF_OVAL ,0, XEC_GMII_TXD_BIT1_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT1_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT2_IOF_OVAL ,0, XEC_GMII_TXD_BIT2_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT2_IOF_OVAL ,0, 0 ,0 ,0);
     iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT3_IOF_OVAL ,0, XEC_GMII_TXD_BIT3_HS_SEL ,0 ,0);
    // iomux_ls_iof_slew_rate(IOMUX_BASE, XEC_GMII_TXD_BIT3_IOF_OVAL ,0, 0 ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT4_IOF_OVAL ,0, XEC_GMII_TXD_BIT4_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT5_IOF_OVAL ,0, XEC_GMII_TXD_BIT5_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT6_IOF_OVAL ,0, XEC_GMII_TXD_BIT6_HS_SEL ,0 ,0);
    // iomux_iof_oval_cfg(IOMUX_BASE, XEC_GMII_TXD_BIT7_IOF_OVAL ,0, XEC_GMII_TXD_BIT7_HS_SEL ,0 ,0);

    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT0_IOF_OVAL ,0, XEC_GMII_RXD_BIT0_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT1_IOF_OVAL ,0, XEC_GMII_RXD_BIT1_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT2_IOF_OVAL ,0, XEC_GMII_RXD_BIT2_HS_SEL ,0 ,0);
    iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT3_IOF_OVAL ,0, XEC_GMII_RXD_BIT3_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT4_IOF_OVAL ,0, XEC_GMII_RXD_BIT4_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT5_IOF_OVAL ,0, XEC_GMII_RXD_BIT5_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT6_IOF_OVAL ,0, XEC_GMII_RXD_BIT6_HS_SEL ,0 ,0);
    // iomux_iof_ival_cfg(IOMUX_BASE, XEC_GMII_RXD_BIT7_IOF_OVAL ,0, XEC_GMII_RXD_BIT7_HS_SEL ,0 ,0);
    ////////////////////yhf
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_0_IOF_IVAL,39,LGPIO_IO_PORT_PINS_0_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_1_IOF_IVAL,40,LGPIO_IO_PORT_PINS_1_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_2_IOF_IVAL,35,LGPIO_IO_PORT_PINS_2_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_3_IOF_IVAL,36,LGPIO_IO_PORT_PINS_3_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,37,LGPIO_IO_PORT_PINS_4_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,38,LGPIO_IO_PORT_PINS_5_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,33,LGPIO_IO_PORT_PINS_6_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,34,LGPIO_IO_PORT_PINS_7_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_3_IOF_IVAL,0,LGPIO_IO_PORT_PINS_3_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_4_IOF_IVAL,1,LGPIO_IO_PORT_PINS_4_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_5_IOF_IVAL,2,LGPIO_IO_PORT_PINS_5_HS_SEL,0,0);
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_24_IOF_IVAL,158,LGPIO_IO_PORT_PINS_24_HS_SEL,0,0);   
    // iomux_ls_iof_ival_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_25_IOF_IVAL,159,LGPIO_IO_PORT_PINS_25_HS_SEL,0,0);
    ////////////////////yhf
}

/*
 * 设置指定GPIO的模式
 *
 * slave_num  需要操作的从机设备
 * gpio_port  gpio端口  端口0/1
 * gpio_num   哪一个GPIO
 *
 * 返回值：void
 * */
void nca9555_set_output_mode(uint8_t slave_num, uint8_t gpio_port,  uint8_t gpio_num)
{
    uint8_t register_original_data = 0;
    if(gpio_port > 1 || gpio_num > 0x80)  return;
    if(gpio_port == 0)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, CONFIG_PORT_REGISTER0, &register_original_data);
        nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, CONFIG_PORT_REGISTER0, register_original_data & (~gpio_num));
    }
    else if(gpio_port == 1)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, CONFIG_PORT_REGISTER1, &register_original_data);
        nca9555_write_byte( slave_num | HOST_WRITE_COMMAND, CONFIG_PORT_REGISTER1, register_original_data & (~gpio_num));
    }
}

/*
 * 设置GPIO为输入模式
 *
 * slave_num  需要操作的从机设备
 * gpio_port  gpio端口  端口0/1
 * gpio_num   哪一个GPIO
 *
 * 返回值：void
 **/
void nca9555_set_input_mode(uint8_t slave_num, uint8_t gpio_port,  uint8_t gpio_num)
{
    uint8_t register_original_data = 0;
    if(gpio_port > 1 || gpio_num > 0x80)  return;
    if(gpio_port == 0)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, CONFIG_PORT_REGISTER0, &register_original_data);
        nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, CONFIG_PORT_REGISTER0, register_original_data & gpio_num);
    }
    else if(gpio_port == 1)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, CONFIG_PORT_REGISTER1, &register_original_data);
        nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, CONFIG_PORT_REGISTER1, register_original_data & gpio_num);
    }
}

/*
 * 设置GPIO输出状态
 *
 * slave_num  需要操作的从机设备
 * gpio_port  gpio端口  端口0/1
 * gpio_num   哪一个GPIO
 * status     输出状态
 *
 * 返回值：void
 **/
void nca9555_set_gpio_output_status(uint8_t slave_num, uint8_t gpio_port,  uint8_t gpio_num, uint8_t status)
{
    uint8_t register_original_data = 0;
    if(gpio_port > 1 || gpio_num > 0x80)  return;
    if(gpio_port == 0)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, OUTPUT_PORT_REGISTER0, &register_original_data);
        if(status == 1)
        {
            nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, OUTPUT_PORT_REGISTER0, register_original_data | gpio_num);
        }
        else
        {
            nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, OUTPUT_PORT_REGISTER0, register_original_data & (~gpio_num));
        }
    }
    else if(gpio_port == 1)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, OUTPUT_PORT_REGISTER1, &register_original_data);
        if(status == 1)
        {
            nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, OUTPUT_PORT_REGISTER1, register_original_data | gpio_num);
        }
        else
        {
            nca9555_write_byte(slave_num | HOST_WRITE_COMMAND, OUTPUT_PORT_REGISTER1, register_original_data & (~gpio_num));
        }
    }
}

/*
 * 获取GPIO状态
 *
 * slave_num  需要操作的从机设备
 * gpio_port  gpio端口  端口0/1
 * gpio_num   哪一个GPIO
 *
 * 返回值：GPIO状态
 **/
uint8_t nca9555_get_gpio_status(uint8_t slave_num, uint8_t gpio_port,  uint8_t gpio_num)
{
    uint8_t register_original_data = 0;
    uint8_t gpio_status = 0;
    if(gpio_port > 1 || gpio_num > 0x80)
    {
        printf("[ERROR] gpio_port > 1 || gpio_num > 0x80\r\n");
        return 2;
    }
    if(gpio_port == 0)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, INPUT_PORT_REGISTER0, &register_original_data);
    }
    else if(gpio_port == 1)
    {
        nca9555_read_byte(slave_num, slave_num  | HOST_READ_COMMAND, INPUT_PORT_REGISTER1, &register_original_data);
    }
    switch(gpio_num)
    {
        case 0x01:  gpio_status = register_original_data & gpio_num;break;
        case 0x02:  gpio_status = (register_original_data & gpio_num) >> 1;break;
        case 0x04:  gpio_status = (register_original_data & gpio_num) >> 2;break;
        case 0x08:  gpio_status = (register_original_data & gpio_num) >> 3;break;
        case 0x10:  gpio_status = (register_original_data & gpio_num) >> 4;break;
        case 0x20:  gpio_status = (register_original_data & gpio_num) >> 5;break;
        case 0x40:  gpio_status = (register_original_data & gpio_num) >> 6;break;
        case 0x80:  gpio_status = (register_original_data & gpio_num) >> 7;break;
        default:  printf("[ERROR] gpio error!\r\n");
    }
    return gpio_status;
}


void fpga_gpio_init(void)
{
	lgpio_clk_en(ENABLE);
	lgpio_set_rst(DISABLE);
	lgpio_set_rst(ENABLE);

	//107引脚  FPGA1_DI
	//配置FPGA1_DI引脚为LGPIO16输出
	iomux_ls_iof_oval_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_16_IOF_OVAL,100,LGPIO_IO_PORT_PINS_16_HS_SEL,0,0);
	
	//使能LGPIO16
	LGPIO_Output_Enable(LGPIO,1<<16);
	
	//LGPIO16写1
	LGPIO_WriteBit(LGPIO,1<<16,1);
	
	//LGPIO16上拉
	LGPIO_Mode(LGPIO,1<<16,PP);
	
	
	//108引脚  FPGA_CFGCLK
	//配置FPGA_CFGCLK引脚为LGPIO17输出
	iomux_ls_iof_oval_cfg(IOMUX_BASE,LGPIO_IO_PORT_PINS_17_IOF_OVAL,101,LGPIO_IO_PORT_PINS_17_HS_SEL,0,0);
	
	//使能LGPIO17
	LGPIO_Output_Enable(LGPIO,1<<17);
	
	//LGPIO17写1
	LGPIO_WriteBit(LGPIO,1<<17,1);
	
	//LGPIO17上拉
	LGPIO_Mode(LGPIO,1<<17,PP);
	

	nca9555_set_output_mode(PCA9555_ADDR, GPIO_PORT0, CARD_RST_PORT);

	nca9555_set_output_mode(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD2_PORT);
	nca9555_set_output_mode(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD1_PORT);
	nca9555_set_output_mode(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD0_PORT);	


}

void pre_init(void)
{
	//时钟使能：
	i2c1_clk_en(ENABLE);
	i2c1_set_rst(DISABLE);
	i2c1_set_rst(ENABLE);
	
	//IIC1引脚初始化：
	iomux_ls_iof_oval_cfg(IOMUX_BASE, I2C1_SCL_IOF_OVAL, 60, I2C1_SCL_HS_SEL, 0, 0);
	iomux_ls_iof_oval_cfg(IOMUX_BASE, I2C1_SDA_IOF_OVAL, 61, I2C1_SDA_HS_SEL, 0, 0);
	iomux_ls_iof_pullup_cfg(IOMUX_BASE, 60, I2C1_SCL_HS_SEL, 0, 0);
	iomux_ls_iof_pullup_cfg(IOMUX_BASE, 61, I2C1_SDA_HS_SEL, 0, 0);
	iomux_ls_iof_ival_cfg(IOMUX_BASE, I2C1_SCL_IOF_IVAL, 60, I2C1_SCL_HS_SEL, 0, 0);
	iomux_ls_iof_ival_cfg(IOMUX_BASE, I2C1_SDA_IOF_IVAL, 61, I2C1_SDA_HS_SEL, 0, 0);
	
	//先初始化IIC1后初始化PCA9555:
	IIC_config();
	Pca9555Init();
}

void set_fpga_slave_serial(void)
{
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD2_PORT, 1);
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD1_PORT, 1);
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT1, CARD1_CFGMD0_PORT, 1);	
}

int do_serial_send_byte(uint8 data)
{
	int i;
	
	LGPIO_WriteBit(LGPIO,1<<17,0);
	for (i=0; i<8; i++)
	{
		LGPIO_WriteBit(LGPIO,1<<16, (data>>(7-i)) & 0x01);
		LGPIO_WriteBit(LGPIO,1<<17,1);

		//mydelay();
		LGPIO_WriteBit(LGPIO,1<<17,0);
		//mydelay();
	}

	return 0;
}


void reset_fpga()
{	
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT0, CARD_RST_PORT, 1);
	delay_1ms(1);
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT0, CARD_RST_PORT, 0);	
	
	set_fpga_slave_serial();////set fpga mode:slave serial
	
	delay_1ms(1);
	nca9555_set_gpio_output_status(PCA9555_ADDR, GPIO_PORT0, CARD_RST_PORT, 1);
	delay_1ms(1);
}
#ifdef __cplusplus
#if __cplusplus
extern "C" {
#endif /* __cpluscplus */
#endif /* __cpluscplus */

static UINT32 g_uwTskHiID;
static UINT32 g_uwTskLoID;
static UINT8 FPGA_upgrade_flag=0;
UINT32 Temp_value=0;
#define TSK_PRIOR_HI 4
#define TSK_PRIOR_LO 5

uint8 FPGAReadBuffer[256]={0};
static UINT32 do_serial_fpga_load(VOID)
{
	uint32 i,j;
    while(1)
    {
        if(FPGA_upgrade_flag==0)
        {
            dprintf("\r\n3. send '0xAA' to upgrade fpga, send '0x55' to skip test!\r\n");
        }
        Temp_value=(USART0->RXDATA);
        if(Temp_value& USART_RXDATA_EMPTY)
        {
            Temp_value=0;
        }
        else
        {
            Temp_value=(Temp_value & 0xFF);
        }
        // Temp_value=((USART0->RXDATA)& 0xFF);
        if((Temp_value==0xAA)&&(FPGA_upgrade_flag==0))
        {
            dprintf("\r\n4. fpga upgrade start!\r\n");
            pre_init(); //init i2c、pca9555
            dprintf("\r\n5. pre_init();!\r\n");
            fpga_gpio_init(); //init fpga gpio
            dprintf("\r\n6. fpga_gpio_init();!\r\n");
            reset_fpga(); //reset fpga
            dprintf("\r\n7. reset_fpga();!\r\n");
            spi_flash_init();
            dprintf("\r\n8. spi_flash_init();!\r\n");
            for (i=0; i<7941; i++)
            {
                spi_flash_buffer_read(FPGAReadBuffer,i*256,256);
                for (j=0; j<256; j++)
                {		
                    // printf("0x%02x ",FPGAReadBuffer[j]);
                    do_serial_send_byte(FPGAReadBuffer[j]);
                }
            }

            spi_flash_buffer_read(FPGAReadBuffer,7941*256,20);
            for (j=0; j<20; j++)
            {		
                // printf("0x%02x ",FPGAReadBuffer[j]);
                do_serial_send_byte(FPGAReadBuffer[j]);
            }
            // for (i=0; i<fpga_len; i++)
            // {		
            // 	do_serial_send_byte(*fpga_addr);
            // 	fpga_addr++;
            // }
            FPGA_upgrade_flag=1;
            dprintf("\r\n9. fpga upgrade success!\r\n");
        }
        else if((Temp_value==0xAA)&&(FPGA_upgrade_flag==1))
        {
            FPGA_upgrade_flag=0;
            Temp_value=0;
            LOS_InspectStatusSetByID(LOS_INSPECT_FPGA,LOS_INSPECT_STU_SUCCESS);
            LOS_TaskDelete(g_uwTskHiID);
            LOS_TaskDelete(g_uwTskLoID);
            return LOS_OK;
        }
        else if(Temp_value==0x55)
        {
            FPGA_upgrade_flag=0;
            Temp_value=0;
            LOS_InspectStatusSetByID(LOS_INSPECT_FPGA,LOS_INSPECT_STU_SUCCESS);
            LOS_TaskDelete(g_uwTskHiID);
            LOS_TaskDelete(g_uwTskLoID);
            return LOS_OK;
        }
        Temp_value=0;
        LOS_TaskDelay(1000);
    }
}
extern int link_main(void *args);
UINT32 Example_FPGA(VOID)
{
    UINT32 uwRet;
    TSK_INIT_PARAM_S stInitParam;
    dprintf("\r\n--------4.18 FPGA upgrade test start!--------\r\n");
    /* lock task shcedue */
    LOS_TaskLock();

    stInitParam.pfnTaskEntry = (TSK_ENTRY_FUNC)link_main;
    stInitParam.usTaskPrio = TSK_PRIOR_HI;
    stInitParam.pcName = "link_test";
    stInitParam.uwStackSize = 0x1000;
    /* create high prio task */
    uwRet = LOS_TaskCreate(&g_uwTskHiID, &stInitParam);
    if (uwRet != LOS_OK)
    {
        LOS_TaskUnlock();

        dprintf("\r\nlink_test create Failed!\r\n");
        return LOS_NOK;
    }

    dprintf("\r\n1. link_test create Success!\r\n");

    stInitParam.pfnTaskEntry = (TSK_ENTRY_FUNC)do_serial_fpga_load;
    stInitParam.usTaskPrio = TSK_PRIOR_LO;
    stInitParam.pcName = "link_fpga";
    stInitParam.uwStackSize = 0x1000;
    /* create low prio task */
    uwRet = LOS_TaskCreate(&g_uwTskLoID, &stInitParam);
    if (uwRet != LOS_OK)
    {
        LOS_TaskUnlock();

        dprintf("\r\ndo_serial_fpga_load create Failed!\r\n");
        return LOS_NOK;
    }
    dprintf("\r\n2. do_serial_fpga_load create Success!\r\n");
    lwip_iomux_cfg();
    /* unlock task schedue */
    LOS_TaskUnlock();

    return uwRet;
}

#ifdef __cplusplus
#if __cplusplus
}
#endif /* __cpluscplus */
#endif /* __cpluscplus */
